MIT Researchers Shows off 36 Core CPU with “network-on-chip”

Last week, at the International Symposium on Computer Architecture, MIT research group unveiled 36 core chip. What’s new about this chip is the way it communicates with its cores – it is called “network-on-chip”.

Today’s multicore CPUs are connecting and communicating with its multiple cores with single wire, called bus, when two cores are needed to communicated, they are given access to the bus. This will become an issue as the number of cores increases, because then time to wait for the access to bus will increase and it will reduced the performance of the chip.

This new technique called “network-on-chip” connects cores only adjacent to each other, therefore creating a network of cores, this allows each cores to have immediate access to the core next to it, and also there are always more than one way to connect two cores – therefore increasing the performance.

This way of “network” connecting creates a new problem on how these cores access data. Every core has its own cache to store recently used data, and when other core needs this data, usually cores send the data back to main memory and again other cores retrieve it, but this is time consuming workflow.

Processor designers use a protocol called “snoopy” to access the data before it is been shipped to memory. It works like this, when a core needs a data, it broadcast the request to all other cores, and whichever core has the data, return the data back. This is particularly easy when all cores shares same single bus, because the request and reply shares the same route and it is easy to track the latest request.

But problem comes when there is a “network” between cores, because almost every single core talks to every other core and it is hard to handle the latest request. MIT team also solved the problem by using secondary network between these cores. This secondary network handles the request and therefore allowing the CPU to work coherently.

MIT researchers also intend to load the CPU with modified version of Linux that is optimized to work with 36 cores and evaluate the real world performance. Also MIT researchers intend to release the blueprint of the chip design as open source core – written in Verilog – hardware description language.

Source: MIT